A digital phase-lock loop DPLL is a device that tracks and extracts the phase of a sampled signal. By way of example, reference may be made to the following three publications which provide a survey of the prior art of digital phase-lock loop technology: A Survey of Digital Phase-Lock Loops by W. C. Lindsey and C. M. Chie, Proceedings of IEEE, volume 69, number 4, page 410, April 1981; Design and Performance of Sampled Data Loops for Subcarrier and Carrier Tracking by S. Acquirre and W. J. Hurd, TDA Progress Report 42-79, page 81, July 1984; and a Comparison of Methods for DPLL Loop-Filter by S. Acquirre and W. J. Hurd, TDA Progress Report 42-87, pp. 114, July, 1986.
The major components of a standard phase-lock loop are a number-controlled oscillator (NCO), a signal counter-rotator, an adder, a phase extractor, and a loop filter. An NCO is a component that generates a sinusoidal output based on phase and phase-rate registers. For each sample point, the phase register is incremented by the value in the rate register and the resulting phase is used to generate sine and cosine values that comprise the NCO phase. The sampled signal is counter-rotated (multiplied) with this NCO phasor and the complex product is accumulated over an interval. A phase extractor produces a measure of the phase of the resulting complex sum and this phase error signal is a measure of the difference of the actual phase and the NCO phase over the interval. The loop filter processes this phase-error value along with previous values to obtain a new estimate of phase rate. This phase-rate value is inserted in the phase-rate register of the NCO in order to improve the rate value in subsequent counter-rotation. Phase is measured at a given time point by reading the NCO phase register at that time point. Integer cycles of NCO phase are obtained with a counter that keeps track of the integer-cycle overflow of the NCO fractional-cycle phase register. Loop lock is obtained by sweeping the NCO phase rate until the signal is acquired.